This paper describes abot the counter scaling design. To enhance the performance and battery of the system To reduce the chip size area and the power consumption, the VLSI circuits are designed at low power, the key elements are scaling design, counter are used to enhance or minimize the values based upon the previous state meanwhile the counting process depends upon the time and frequency must be measured. The power consumption is reduced by decreasing the switching performance. The main disadvantage is scaling circuit of the power consumption because of the clock power dissipation during the standby mode. The total power is assumed by the clock signal that is only one -third of power is consumed.By reducing the power consumption in flip-flops, this is achieved by TSPCL (True single phase clock logic) through the self controllable voltage level (SVP)

Keywords: CMOS,Counter, Synchronous Clock,Low power.