Gordon Moore, the co-founder of Intel, predicted that the number of transistors would quadruple every two years. As a result, device scaling had to happen. Scientists and researchers quickly learned that silicon MOSFETs had a scaling issue with technology. Carbon nanotube field effect transistors (CNTFET) are now replacing silicon metal oxide semiconductor field effect transistors (MOSFET) as an alternative. However, whereas we have access to precise circuit-level equations for MOSFETs, all we have for carbon nanotubes are model equations. In this research, we seek to model the behavior of the SWCNT-FET under varying conditions of diameter and gate insulator thickness. This would allow for more accurate performance predictions from the device, paving the way for more complicated CNTFET based circuit designs. Variations in mobile charges, drain currents, and gate insulator thickness are among the variables investigated. Simulation results demonstrate that the size of CNT diameter has direct influence on drain current which could be potential replacement of silicon technology for digital applications.