Quality gates are check points to ensure that the current product development effort satisfies product requirements. Quality gates are frequently used in product development processes to detect errors and deviations early and thus prevent big and costly rework cycles. Despite their utility, quality gates may lead to significant effort overhead, and too frequent quality checking can significantly increase overall effort and span time in a process. This paper develops a decision support method that uses process modelling and simulation to successfully place quality gates in a process, such that an optimal trade-off can be obtained between rework reduction and checking effort. Process mapping is used to represent activities that occur in a process, the information flow between activities, and likely rework iteration routes. Possible quality gates are identified and quality gate placing scenarios are also built as part of the proposed process mapping method. Simulation is used to evaluate the impact of rework risk associated to each quality gate placing scenario, along with overall quality checking effort that is necessary to undertake the process. Gate placing scenarios are compared based on the estimated process span time and effort. The proposed method is illustrated in a sample product development process.