Modern microchips are now embedded into everything from cars and washing machines to fighter planes. Today silicon chips are everywhere, driving all forms of digital innovation. If anything, the mercurial rise in market demand for microchips understate the importance of chip making. The silicon wafer is a major component in producing integrated circuits, with sizes that vary in thickness from 275 to 925 μm. A hairline crack is a major defect commonly found in thin wafers in the downstream supply chain of the semiconductor industry. Too high a downtime of 19 hours was incurred with the detection of hairline cracks at the wafer sort process that implemented a Cross Crack Check (CCC) at chip probe (CP). In this case of an outsourced assembly and testing (OSAT) company, a DMAIC (Define-Measure-Analyze-Improve-Control) approach was employed in identifying and addressing the root causes of high CCC flag trigger and validated 4 out of 19 major process contributors to hairline-caused downtime of 4.83% which all resulted in an opportunity revenue loss of $57,000. The study presented corrective solutions in reducing CCC flag trigger from 14 to only 4 wafers and consequently minimizing CCC flag downtime level to 1.53% or from 19 to 3 hours.