This paper describes and compares the implementation of different iξk floating point multipliers on the Virtex-4 FPGA platform. VHDL code for the multiplier was developed to implement the multiplier using XILINX ISE design suite version 14.1. Different values of i and k have been used to simulate the multipliers and results for each value of i and k have been tabulated. The results include execution time for calculating the resulting exponent and the resulting mantissa in the final product. Simulation waveforms have also been reported in this paper, and suggestions for future work have been included at the end.
Track: Modeling and Simulation
Published in: 3rd North American International Conference on Industrial Engineering and Operations Management, Washington D.C., USA
Publisher: IEOM Society International
Date of Conference: September 27
-29
, 2018
ISBN: 978-1-5323-5946-0
ISSN/E-ISSN: 2169-8767