Remote Global Alignment Error for Pad Inductor Layer To Improve Cycle Time
Saandilian Devadas
Department of Manufacturing Design
Faculty of Manufacturing Engineering,
Universiti Teknikal Malaysia Melaka,
76100, Durian Tunggal, Melaka, Malaysia
saandilian_devadas@silterra.com
Shajahan Bin Maidin
Department of Manufacturing Design
Faculty of Manufacturing Engineering,
Universiti Teknikal Malaysia Melaka,
76100, Durian Tunggal, Melaka, Malaysia
Tritham Wara
Department of Photo Lithography
Silterra Malaysia Sdn. Bhd,
09000, Kulim, Kedah, Malaysia
Nurul Ayu Binti Hashim
Department of Photo Lithography
Silterra Malaysia Sdn. Bhd,
09000, Kulim, Kedah, Malaysia
Leng Kok Hong
Department of CIM - ES
Silterra Malaysia Sdn. Bhd,
09000, Kulim, Kedah, Malaysia
Abstract— Lithography is the key process which transfers the pattern on one mask (reticle) to the resist layer and pad inductor layer is the last layer in photo masking. This cause the cycle time for pad inductor layer increase due to having 32% of Global Alignment (GA) error per month currently at Silterra Malaysia Sdn Bhd. This induce success rate goes down as low as 50%. In the same time, long engineering time is taken to dispose the lot (Exp-Dev-Only) due to tool time availability since this activity needs to be performed by a Process Engineer in manually while few marks were required to be tested to align the wafer. Most of the lots send for rework causing the cost per wafer to increase. The goal of this project is to reduce the cycle time for pad inductor layers by introducing the “Remote Global Alignment Error Method” (RGAE) method with alternative flow. This would avoid the pad inductor layers to be send to rework if it encountered any global alignment error. The experimental result shows that the RGAE method provides fast solution to reduce cycle time for pad inductor layers. This is due when encounter global alignment error, the lot will automatically track in using RGAE script method by selecting the rejected wafers for expose and develop process. This has eventually save more time for split wafers and send for rework or run the lot manually and furthermore, the rework rate falls to 0%.
Keywords—Lithography, Pad Inductor Layer, Remote Global Alignment Error, Rework