Today’s semiconductor manufacturing industry needs to improve its competitiveness by enabling new technologies and capabilities using existing equipments. Literatures show many improvements made in enabling CMOS 0.13µm technology at 0.18µm equipment platform on 200mm. This will avoid the need for additional dedicated equipments, or equipment upgrades. The fabrication process must improve to a level to increase process margin within the product specification. Almost all the capability enhancements need Capital Expenditure (CAPEX). However, enabling new technology through process improvement is the most challenging approach and usually needs very minimum capital expenditure. This paper will discuss real implementation of process improvement that successfully enabled CMOS 0.13µm technology at 0.18µm equipment platform where Shallow Trench Isolation (STI) was a constraint. The approach presented in this paper is through re-design of process development on forming new profile of STI that results in a new physical structure that is able to hold the isolation needed when current flow throughout the chip. This study utilized dataPower yield management system application, wafer position method, inline data collection and process matching.  The results were successfully implemented to enable the capability for CMOS 0.13µm technology in existing factory and minimize CAPEX for 200mm semiconductor manufacturing.