Complementary Metal Oxide Semiconductor (CMOS) is a complex and very delicate process in semiconductor. In typical 30,000 wafer capacity of single foundry business model, the CMOS product loads are mixed from various technologies to serve wider market segments. Total devices can be ranged from 100 to 200. This approach creates variables for process time, equipment usage, number of processing steps which leads to inconsistent WIP profiling at respective time period. A simple indication bar chart to indicate WIP quantity profile at each step is not able to indicate the overall cycle time status of WIP. Literature discussed method needed to apply for WIP planning, but limited for WIP monitoring approaches. This paper is a research regards new approach to develop WIP monitoring parameters that able to show current WIP performance, DPML performance, current WIP to allow strategy to improve WIP planning that resulted for optimize output at effective cycle time. This paper will illustrated the arithmetic for WIP parameter and real case study of approach used from the parameters in the WIP profile data to output and cycle time improvement. The benefits of this information has successfully directed to new WIP strategy that improve the quarterly output by 10% and cycle time at reasonable cycle time.

Keyword: Day per Mask Layer (DPML), Work In Progress (WIP), WIP profile, CMOS, Foundry