4th Asia Pacific International Conference on Industrial Engineering and Operations Management

A Study on Order Release Control Policies in Wafer Fabrication Facility: A Review, Classification and Conceptual Simulation Framework

RAGUPATHI T & Muthu Mathirajan
Publisher: IEOM Society International
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Track: Operations Management
Abstract

The manufacturing of semiconductor chips consists of a four-stage process: wafer fabrication or processing, sort or probe, assembly, and test. Out of four stages, wafer fabrication, which necessitates a large amount of investment in plant and equipment, is probably the most complicated manufacturing process today. In addition, wafer fabrication complexity is caused by many factors, including unrelated parallel machines, batch machines, uncertain process yields, re-entrant process flows, random equipment failures, and process variability. Maintaining a competitive advantage and remaining profitable in operational terms requires improvements in wafer fab performance. Workload Control (WC), a combination of Order Release Control (ORC) and Dispatching Control (DC), is employed to regulate the flow of orders through the wafer fab, and this is a promising technique to reduce the wafer’s processing cost and increase customer satisfaction by delivering products on time. Particularly, ORC is considered a critical operational control strategy in wafer fab as it controls the system's WIP and meets due dates. Hence, to properly understand ORC policies, this study meticulously reviews the existing studies on ORC in wafer fabrication. Based on the literature analysis, the existing ORC policies are classified considering eight dimensions that describe fundamental characteristics and logic behind the ORC policies and possible suggestions are presented for future work. Further, this study presents a discrete event simulation (DES) based conceptual model framework for the performance assessment of any ORC policies with various performance measures such as average cycle time, average throughput, WIP level and number of tardy jobs. The proposed DES model can capture the complexities in the wafer fabs, such as re-entrance, non-identical parallel machines, and rework, in a very effective manner. Finally, the proposed framework is expected to improve the efficiency of the DES model as it reduces the preparation time for input data and is also flexible to emulate random scenarios with uncertain processing times, product mix and product routes.

Published in: 4th Asia Pacific International Conference on Industrial Engineering and Operations Management, Vietnam

Publisher: IEOM Society International
Date of Conference: September 12-14, 2023

ISBN: 979-8-3507-0548-5
ISSN/E-ISSN: 2169-8767